Shifting Bit Patterns

Name:

SL $X,$Y,$Z	SL $X,$Y,Z
SLU $X,$Y,$Z	SLU $X,$Y,Z
SR $X,$Y,$Z	SR $X,$Y,Z
SRU $X,$Y,$Z	SRU $X,$Y,Z

Specification:

SL: s($X) ← s($Y) × 2^u($Z)
SLU: u($X) ← (u($Y) × 2^u($Z)) mod 2⁶⁴
SR: s($X) ← ⌊s($Y) / 2^u($Z)⌋
SRU: u($X) ← ⌊u($Y) / 2^u($Z)⌋

Timing:

1υ

Description:

SL shifts the bits in register $Y left. If bits unequal to the sign bit of $Y are shifted out during this process, an overflow is signaled. The result is filled with 0 bits from the right. SLU has the same effect but never causes overflow.

SR shifts the bits in register $Y to the right. It fills the target register from the left by replicating the sign bit and discards bits on the right; SRU fills the target register from the left with zeros.

SL: The bits of register $Y are shifted left by $Z or Z places, and 0s are shifted in from the right; the result is placed in register $X. Register $Y is treated as a signed number, but the second operand is treated as an unsigned number. The effect is the same as multiplication by 2^$Z or by 2^Z; an integer overflow exception occurs if the result is - 2⁶³ or < -2⁶³. In particular, if the second operand is 64 or more, register $X will become entirely zero, and integer overflow will be signaled unless register Y was zero.

SLU: The bits of register $Y are shifted left by $Z or Z places, and 0s are shifted in from the right; the result is placed in register $X. Both operands are treated as unsigned numbers. The SLU instructions are equivalent to SL, except that no test for overflow is made.

SR: The bits of register Y are shifted right by $Z or Z places, and copies of the leftmost bit (the sign bit) are shifted in from the left; the result is placed in register X. Register Y is treated as a signed number, but the second operand is treated as an unsigned number. The effect is the same as division by 2^$Z or by 2^Z and rounding down. In particular, if the second operand is 64 or more, register $X will become zero if $Y was nonnegative, -1 if $Y was negative.

SRU: The bits of register $Y are shifted right by $Z or Z places, and 0s are shifted in from the left; the result is placed in register $X. Both operands are treated as unsigned numbers. The effect is the same as unsigned division of a 64-bit number by 2^$Z or by 2^Z; if the second operand is 64 or more, register $X will become entirely zero.

SL: s($X)	← s($Y) × 2^u($Z)
SLU: u($X)	← (u($Y) × 2^u($Z)) mod 2⁶⁴
SR: s($X)	← ⌊s($Y) / 2^u($Z)⌋
SRU: u($X)	← ⌊u($Y) / 2^u($Z)⌋

SL:	The bits of register $Y are shifted left by $Z or Z places, and 0s are shifted in from the right; the result is placed in register $X. Register $Y is treated as a signed number, but the second operand is treated as an unsigned number. The effect is the same as multiplication by 2^$Z or by 2^Z; an integer overflow exception occurs if the result is - 2⁶³ or < -2⁶³. In particular, if the second operand is 64 or more, register $X will become entirely zero, and integer overflow will be signaled unless register Y was zero.
SLU:	The bits of register $Y are shifted left by $Z or Z places, and 0s are shifted in from the right; the result is placed in register $X. Both operands are treated as unsigned numbers. The SLU instructions are equivalent to SL, except that no test for overflow is made.
SR:	The bits of register Y are shifted right by $Z or Z places, and copies of the leftmost bit (the sign bit) are shifted in from the left; the result is placed in register X. Register Y is treated as a signed number, but the second operand is treated as an unsigned number. The effect is the same as division by 2^$Z or by 2^Z and rounding down. In particular, if the second operand is 64 or more, register $X will become zero if $Y was nonnegative, -1 if $Y was negative.
SRU:	The bits of register $Y are shifted right by $Z or Z places, and 0s are shifted in from the left; the result is placed in register $X. Both operands are treated as unsigned numbers. The effect is the same as unsigned division of a 64-bit number by 2^$Z or by 2^Z; if the second operand is 64 or more, register $X will become entirely zero.